In response to a recent need for energy-saving, a technology for accurately detecting current with a low loss has become more important. A method for accurately detecting current with a low loss is disclosed in JP-A-2003-28901, for example.
JP-A-2003-28901 discloses a method for accurately detecting load current using a multi-source MOS as shown in FIG. 10. A multi-source MOS 2 includes a load driving MOS Q1 for controlling current to flow through a load 4 and a current detection MOS Q2 for detecting the current. The current detection MOS Q2 is formed on the same chip with the load driving MOS Q1. The structures of the current detection MOS Q2 and the load driving MOS Q1 are the same but the areas of the current detection MOS Q2 and the load driving MOS Q1 are different. A current detection circuit 3 includes an amplifier AMP, a transistor TR and a resistor R. Since the amplifier AMP controls the transistor TR so that the source voltage of the load driving MOS Q1 is equal to the source voltage of the current detection MOS Q2, the current flowing through the current detection MOS Q2 becomes a ratio of on-resistance of the load driving MOS Q1 and the current detection MOS Q2. The ratio of on-resistance is inversely proportional to a ratio of the chip size of the load driving MOS Q1 and the current detection MOS Q2.
JP-A-2003-28901 discloses that a current detection error of the current detection circuit 3 due to the offset voltage of the amplifier AMP is dependent on the current flowing through the load 4 and a means for reducing the influence of the offset voltage is provided. According to JP-A-2003-28901, in a case where the current flowing through the load 4 is large, the source-drain voltage of the load driving MOS Q1 and the current detection MOS Q2 is large and therefore the current detection voltage is increased. Accordingly, the influence of the offset voltage of the amplifier AMP is relatively small.
However, in a case where the current flowing through the load 4 is small, the source-drain voltage of the load driving MOS Q1 and the current detection MOS Q2 is also small, that is, the current detection voltage is small. Accordingly, the offset voltage of the amplifier AMP is not negligible and thus the current detection accuracy is degraded. JP-A-2003-28901 suggests a means for varying on-resistance of the load driving MOS Q1 in accordance with the current flowing through the load 4, in order to solve the situation.
Further, JP-A-2003-28901 suggests a means for canceling the offset voltage of the amplifier AMP by performing the current detection measurement twice and calculating the difference between the detection results.
FIG. 11 shows a fifth illustrative embodiment of JP-A-2003-28901. The load driving MOS Q1 uses two values of 1:0.5 as the on-resistance of the multi-source MOS. This is enabled by selectively setting a gate voltage applied to the multi-source MOS 2 from an output MOS control circuit 1. According to JP-A-2003-28901, the on-resistance of the load driving MOS is varied to 1 and 0.5 and the current flowing through the current detection MOS Q2 during each of the on-resistance is respectively detected. And, the offset voltage of the amplifier is calculated from the detection results and cancelled.
When a ratio of the on-resistance of the current detection MOS Q2 and the load driving MOS Q1 is indicated as “n”, the offset voltage is indicated as “Voff” and the load current is indicated as “I”, the current Iout1 to be detected by setting the on-resistance of the load driving MOS Q1 as the on-resistance of the ratio “1” in the first current measurement is represented by the following formula.Iout1=(I×on-resistance+Voff)/(n×on-resistance)  (1)Next, the current Iout2 to be detected by setting the on-resistance of the load driving MOS Q1 as the on-resistance of the ratio “0.5” is represented by the following formula.Iout2=(I×0.5 on-resistance+Voff)/(n×0.5 on-resistance)  (2)The detection current Iout to cancel the offset voltage can be obtained by subtracting the load current Iout1 and Iout2.Iout=(2×Iout1-Iout2)/n  (3)